This index covers all technical items—papers, correspondence, reviews, etc.—that appeared in this periodical during 2020, and items from previous years that were commented upon or corrected in 2020. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbrevia- tion, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, mo

This index covers all technical items—papers, correspondence, reviews, etc.—that appeared in this periodical during 2020, and items from previous years that were commented upon or corrected in 2020. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbrevia- tion, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, mo

Coarse-Grained Reconfigurable Architectures (CGRAs) offer a tradeoff between the flexibility of General Purpose Processors (GPPs) and the performance and energy efficiency of Application Specific Integrated Circuits (ASICs). Hence, these CGRAs are used as an appealing platform to accelerate the compute-intensive applications, especially the streaming-based applications such as multimedia processing and signal processing. However, most of these streaming applications are inherently errorresilient, while state-of-the-art CGRAs only support exact computations. In this paper, we present an energy-efficient Approximate Coarse-Grained Reconfigurable Architecture (XCGRA). Instead of conventional exact arithmetic units, it employs configurable appr

In this paper, a low energy consumption block-based carry speculative approximate adder is proposed. Its structure is based on partitioning the adder into some non-overlapped summation blocks whose structures may be selected from both the carry propagate and parallel-prefix adders. Here, the carry output of each block is speculated based on the input operands of the block itself and those of the next block. In this adder, the length of the carry chain is reduced to two blocks (worst case), where in most cases only one block is employed to calculate the carry output leading to a lower average delay. In addition, to increase the accuracy and reduce the output error rate, an error detection and recovery mechanism is proposed. The effectiveness

An energy-quality scalable coarse grain reconfigurable architecture (CGRA) based on the voltage overscaling (VOS) technique is presented. The approximation level of each processing element (PE) in the CGRA is determined by the applied VOS-determined voltage level. By employing the technique, the architecture may be configured for accurate or approximate modes of computation depending on a user-specified output quality-of-service target for a given application. More precisely, operating voltages used for performing various operations in the application dataflow graph are minimized subject to the output quality constraint by using an energy-quality tradeoff algorithm. To make the hardware implementation of the scheme more efficient, PEs are c

This paper presents a methodology for designing an approximate coarse-grained reconfigurable architecture (X-CGRA), and its use for accelerating both error-resilient and error-sensitive applications. The output quality of the X-CGRA is manageable at the run-time for better performance and power/energy consumption tradeoffs. Results show up to 1.9? speedup and 2.3? lower energy consumption at the cost of 9.7% accuracy loss for the studied applications.

In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower accuracy. Each of these compressors has its own level of accuracy in the approximate mode as well as different delays and power dissipations in the approximate and exact modes. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The efficiencies of these compressors in a 32-bit Dadda multiplier are evaluated in a 45-nm standard CMOS tec

In this brief, we propose a fast yet energy-efficient reconfigurable approximate carry look-ahead adder (RAP-CLA). This adder has the ability of switching between the approximate and exact operating modes making it suitable for both error-resilient and exact applications. The structure, which is more area and power efficient than state-of-the-art reconfigurable approximate adders, is achieved by some modifications to the conventional carry look ahead adder (CLA). The efficacy of the proposed RAP-CLA adder is evaluated by comparing its characteristics to those of two state-of-the-art reconfigurable approximate adders as well as the conventional (exact) CLA in a 15 nm FinFET technology. The results reveal that, in the approximate operating mo

With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger’s safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy (HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator